<?xml version="1.0" encoding="utf-8" ?> <rss version="2.0" xmlns:opensearch="http://a9.com/-/spec/opensearch/1.1/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:atom="http://www.w3.org/2005/Atom"> <channel> <title> <![CDATA[ Search for 'su:&quot;Verilog computer hardware description language&quot;']]> </title> <link> https://catalog.riphah.edu.pk//cgi-bin/koha/opac-search.pl?q=ccl=su%3A%22Verilog%20computer%20hardware%20description%20language%22&#38;sort_by=relevance&#38;format=rss </link> <atom:link rel="self" type="application/rss+xml" href="https://catalog.riphah.edu.pk//cgi-bin/koha/opac-search.pl?q=ccl=su%3A%22Verilog%20computer%20hardware%20description%20language%22&#38;sort_by=relevance&#38;format=rss"/> <description> <![CDATA[ Search results for 'su:&quot;Verilog computer hardware description language&quot;' at ]]> </description> <opensearch:totalResults>2</opensearch:totalResults> <opensearch:startIndex>0</opensearch:startIndex> <opensearch:itemsPerPage>50</opensearch:itemsPerPage> <atom:link rel="search" type="application/opensearchdescription+xml" href="https://catalog.riphah.edu.pk//cgi-bin/koha/opac-search.pl?q=ccl=su%3A%22Verilog%20computer%20hardware%20description%20language%22&#38;sort_by=relevance&#38;format=opensearchdescription"/> <opensearch:Query role="request" searchTerms="q%3Dccl%3Dsu%253A%2522Verilog%2520computer%2520hardware%2520description%2520language%2522" startPage="" /> <item> <title> Fundamentals of HDL </title> <dc:identifier>ISBN:9788184314052 (pbk)</dc:identifier> <link>https://catalog.riphah.edu.pk//cgi-bin/koha/opac-detail.pl?biblionumber=12127</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/8184314051.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Godse, Atul P. | Deepali A. Godse.<br /> Pune Technical Publications Pune 2009 .<br /> xviii, Various pages , Includes index. ; 24 cm..<br /> 9788184314052 (pbk) </p> ]]> <![CDATA[ <p> <a href="https://catalog.riphah.edu.pk//cgi-bin/koha/opac-reserve.pl?biblionumber=12127">Place hold on <em>Fundamentals of HDL</em></a> </p> ]]> </description> <guid>https://catalog.riphah.edu.pk//cgi-bin/koha/opac-detail.pl?biblionumber=12127</guid> </item> <item> <title> Verilog digital system design Registered transfer level synthesis, testbench and verification </title> <dc:identifier>ISBN:9780070252219 (pbk)</dc:identifier> <link>https://catalog.riphah.edu.pk//cgi-bin/koha/opac-detail.pl?biblionumber=21430</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/0070252211.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Navabi Zainalabedin.<br /> New Delhi McGraw Hill Education Private Limited 2008 .<br /> xvi, 384 p. , Includes index. ; 22 cm..<br /> 9780070252219 (pbk) </p> ]]> <![CDATA[ <p> <a href="https://catalog.riphah.edu.pk//cgi-bin/koha/opac-reserve.pl?biblionumber=21430">Place hold on <em>Verilog digital system design</em></a> </p> ]]> </description> <guid>https://catalog.riphah.edu.pk//cgi-bin/koha/opac-detail.pl?biblionumber=21430</guid> </item> </channel> </rss>
