Defect-oriented testing for nano-metric CMOS VLSI circuits
Sachdev, Manoj Jose Pineda de Gyvez
Defect-oriented testing for nano-metric CMOS VLSI circuits - New Delhi Springer 2007 - xxi, 328 p. : ill. ; 22 cm.
Includes bibliographical references and index.
9788184894295 (pbk)
Integrated circuits--Very large scale
integration--Defects--Metal oxide semiconductors--Engineering--Systems engineering--Electronics--Engineering design--CMOS fault--SRAM test--Yield engineering--FEAS
621.39732 / SAC
Defect-oriented testing for nano-metric CMOS VLSI circuits - New Delhi Springer 2007 - xxi, 328 p. : ill. ; 22 cm.
Includes bibliographical references and index.
9788184894295 (pbk)
Integrated circuits--Very large scale
integration--Defects--Metal oxide semiconductors--Engineering--Systems engineering--Electronics--Engineering design--CMOS fault--SRAM test--Yield engineering--FEAS
621.39732 / SAC