Design through verilog HDL (Record no. 15728)
[ view plain ]
| 000 -LEADER | |
|---|---|
| fixed length control field | 00596nam a22001457a 4500 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 9788126519316 (pbk) |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.392 |
| Author Mark | PAD |
| 100 ## - MAIN ENTRY--PERSONAL NAME | |
| Authorship | Padmanabhan, T.R. |
| -- | B. Bala Tripura Sundari |
| 245 ## - TITLE STATEMENT | |
| Title | Design through verilog HDL |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) | |
| Place of publication | New Delhi |
| Name of publisher | Wiley India (P.) Ltd. |
| Date of publication | 2013 |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | xii, 455 p. |
| Illustrations | : ill. |
| Dimensions | ; 23 cm. |
| 500 ## - GENERAL NOTE | |
| General note | Includes bibliographical references and index |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Subject | Verilog-Computer hardware description languages |
| Keywords | Switch level modeling |
| -- | Gate level modeling |
| -- | Logic values |
| -- | Language construction |
| -- | Behavioral modeling |
| -- | VLSI design |
| -- | FEAS |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| item type | Books |
| Withdrawn status | Lost status | Damaged status | Not for loan | Home library | Current library | Source of acquisition | Cost, normal purchase price | Full call number | Barcode | Copy number | Koha item type |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Main Campus | Main Campus | Purchased: A2Z Educational Services | 837.00 | 621.392 PAD | 0538 | 1 | Books |