Verilog digital system design Registered transfer level synthesis, testbench and verification

By:

Material type: Text

TextPublication details: New Delhi McGraw Hill Education Private Limited 2008Description: xvi, 384 p. : ill. ; 22 cm. + 1 CDISBN:

Subject(s):

DDC classification:

Tags from this library: No tags from this library for this title. Log in to add tags.

Average rating: 0.0 (0 votes)

Holdings
Item type	Current library	Call number	Copy number	Status	Date due	Barcode
Books	Faisalabad Campus	621.392 NAV (Browse shelf(Opens below))	2	Available		76667
Books	Faisalabad Campus	621.392 NAV (Browse shelf(Opens below))	1	NOT for LOAN		40952

Includes index.

There are no comments on this title.

to post a comment.