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  <titleInfo>
    <title>A system verilog primer</title>
  </titleInfo>
  <name type="personal">
    <namePart>Bhasker, J.</namePart>
    <role>
      <roleTerm authority="marcrelator" type="text">creator</roleTerm>
    </role>
  </name>
  <typeOfResource>text</typeOfResource>
  <originInfo>
    <place>
      <placeTerm type="text">Hyderabad</placeTerm>
    </place>
    <publisher>BS Publications</publisher>
    <dateIssued>2013</dateIssued>
    <issuance>monographic</issuance>
  </originInfo>
  <physicalDescription>
    <extent>xxi, 327 p. : ill. ; 24 cm.</extent>
  </physicalDescription>
  <note>Includes bibliographical references and index.</note>
  <subject>
    <topic>Electronic digital computers</topic>
    <topic>System Verilog</topic>
    <topic>Composite types</topic>
    <topic>Prototypes methods</topic>
    <topic>Operators management</topic>
    <topic>Behavioral modeling</topic>
    <topic>Interprocess communication</topic>
    <topic>FEAS</topic>
  </subject>
  <classification authority="ddc">621.395 BHA</classification>
  <identifier type="isbn">9788178002804 (pbk)</identifier>
  <recordInfo/>
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