Sachdev, Manoj  Jose Pineda de Gyvez <br/><br/>
Defect-oriented testing for nano-metric CMOS VLSI circuits 

 - New Delhi  Springer  2007 
 - xxi, 328 p.  : ill.  ; 22 cm. 
<br/><br/> Includes bibliographical references and index. 
<br/><br/><label>ISBN: </label>9788184894295 (pbk) 
<br/><br/><label>Subjects--Topical Terms: </label><br/>Integrated circuits--Very large scale<br/>integration--Defects--Metal oxide semiconductors--Engineering--Systems engineering--Electronics--Engineering design--CMOS fault--SRAM test--Yield engineering--FEAS
<br/><br/><label>Dewey Class. No.: </label>621.39732  / SAC