using verilog, state machines, and synthesis for FPGAs Lee, Sunggu creator text Andover Cengage Learning 2006 monographic xvii, 462 p. : ill. ; 24 cm. Includes index. Logic circuits Logic design-Data processing VHDL (Computer hardware description language) Optimized implementations Combinational circuits Digital system design VHDL code FEAS 621.395 LEE 9788131518489 (pbk)