Padmanabhan, T.R.  B. Bala Tripura Sundari <br/><br/>
Design through verilog HDL  

 - New Delhi  Wiley India (P.) Ltd.  2013 
 - xii, 455 p.  : ill.  ; 23 cm. 
<br/><br/> Includes bibliographical references and index 
<br/><br/><label>ISBN: </label>9788126519316 (pbk) 
<br/><br/><label>Subjects--Topical Terms: </label><br/>Verilog-Computer hardware description languages --Switch level modeling --Gate level modeling --Logic values --Language construction--Behavioral modeling--VLSI design --FEAS 
<br/><br/><label>Dewey Class. No.: </label>621.392  / PAD