Design through verilog HDL

Design through verilog HDL Padmanabhan, T.R. B. Bala Tripura Sundari creator text New Delhi Wiley India (P.) Ltd. 2013 monographic xii, 455 p. : ill. ; 23 cm. Includes bibliographical references and index Verilog-Computer hardware description languages Switch level modeling Gate level modeling Logic values Language construction Behavioral modeling VLSI design FEAS 621.392 PAD 9788126519316 (pbk)