TY  - BOOK
AU  - Padmanabhan, T.R.
TI  - Design through verilog HDL 
SN  - 9788126519316 (pbk)
U1  - 621.392 
PY  - 2013///
CY  - New Delhi
PB  - Wiley India (P.) Ltd.
KW  - Verilog-Computer hardware description languages
KW  - Switch level modeling
KW  - Gate level modeling
KW  - Logic values
KW  - Language construction
KW  - Behavioral modeling
KW  - VLSI design
KW  - FEAS
N1  - Includes bibliographical references and index
ER  -