00752nam a22001577a 4500020002400000082001700024100004700041245003200088260004300120300003400163500005000197650017900247942000700426952014400433999001700577  a9788126519316 (pbk)  a621.392bPAD  aPadmanabhan, T.R.aB. Bala Tripura Sundari  aDesign through verilog HDL   aNew DelhibWiley India (P.) Ltd.c2013  axii, 455 p.b: ill.c; 23 cm.  aIncludes bibliographical references and index  aVerilog-Computer hardware description languages vSwitch level modeling vGate level modeling vLogic values vLanguage constructionvBehavioral modelingvVLSI design vFEAS   cBK  00104070aRIUbRIUd2016-06-16ePurchased: A2Z Educational Servicesg837.00l0o621.392 PADp0538r2016-06-16 00:00:00t1w2016-06-16yBK  c15728d15728