Navabi Zainalabedin <br/><br/>
Verilog digital system design  Registered transfer level synthesis, testbench and verification 

 - New Delhi  McGraw Hill Education Private Limited  2008 
 - xvi, 384 p.  : ill.  ; 22 cm.  + 1 CD 
<br/><br/> Includes index. 
<br/><br/><label>ISBN: </label>9780070252219 (pbk) 
<br/><br/><label>Subjects--Topical Terms: </label><br/>Verilog computer hardware description language<br/>Electronic digital computer --Verlog sinatation model--Timing devices--Sefuentia analysis--Sorting devices--Hierochical structures--FEAS
<br/><br/><label>Dewey Class. No.: </label>621.392  / NAV