Registered transfer level synthesis, testbench and verification Navabi Zainalabedin creator text New Delhi McGraw Hill Education Private Limited 2008 monographic xvi, 384 p. : ill. ; 22 cm. + 1 CD Includes index. Verilog computer hardware description language Electronic digital computer Verlog sinatation model Timing devices Sefuentia analysis Sorting devices Hierochical structures FEAS 621.392 NAV 9780070252219 (pbk)