TY  - BOOK
AU  - Navabi Zainalabedin
TI  - Verilog digital system design: Registered transfer level synthesis, testbench and verification
SN  - 9780070252219 (pbk)
U1  - 621.392 
PY  - 2008///
CY  - New Delhi
PB  - McGraw Hill Education Private Limited
KW  - Verilog computer hardware description language
KW  - Electronic digital computer
KW  - Verlog sinatation model
KW  - Timing devices
KW  - Sefuentia analysis
KW  - Sorting devices
KW  - Hierochical structures
KW  - FEAS
N1  - Includes index
ER  -