Skahill, Kevin creator text Noida Dorling kindersley Pvt Ltd. 2005, 2018 monographic xiv, 594 p. : ill. ; 24 cm. + CD Includes index. Computer science Digital electronics Synthesis design implementation VHDL design synthesis Programmable logic Architectures Memory controller Optimizing data paths FEAS FC 621.395 SKA 8129704854 (pbk) 9788177587470 (pbk).