TY  - BOOK
AU  - Padmanabhan, T.R.
TI  - Design through verilog HDL 
SN  - 9812531319 (pbk)
U1  - 621.392 
PY  - 2004///
CY  - Canada 
PB  - IEEE Press 
KW  - Verilog-Computer hardware description languages
KW  - VLSI design
KW  - Verilog
KW  - Logic values
KW  - Scalars and vectors
KW  - Switch level modeling
KW  - Behavioural modeling
KW  - FEAS
N1  - Index Included.
ER  -