00678nam a22001577a 4500020002100000082001700021100004000038245003200078260003100110300003400141500002100175650016800196942000700364952013400371999001500505  a9812531319 (pbk)  a621.392bPAD  aPadmanabhan, T.R.aB. Bala Tripura   aDesign through verilog HDL   aCanada bIEEE Press c2004  axii, 455 p.b: ill.c; 22 cm.  aIndex Included.   aVerilog-Computer hardware description languages vVLSI design vVerilog vLogic values vScalars and vectors vSwitch level modeling vBehavioural modeling vFEAS   cBK  00104070aRIUbRIUd2012-08-07ePurchased: Vanguard Booksg354.00l0o621.392 PADp4081r2012-08-07 00:00:00t1w2019-02-21yBK  c3615d3615