| 000 | 00649nam a22001577a 4500 | ||
|---|---|---|---|
| 020 | _a9789380501550 (pbk) | ||
| 020 | _a9780123705976 (pbk) | ||
| 082 |
_a621.395 _bVLS |
||
| 100 |
_aLaung-Terng Wang (editor) _aCheng-Wen Wu (editor) _aXiaoqing Wen (editor) |
||
| 245 |
_aVLSI test principles and architectures _bdesign for test ability |
||
| 260 |
_aNew Delhi _bElsevier _c2013 |
||
| 300 |
_axxx, 777 p. _b: ill. _c; 24 cm. |
||
| 500 | _aIncludes bibliographical references and index. | ||
| 650 |
_aVLSI _aDesign for test ability _vVLSI life-cycle _vlevel of abstraction in VLSI _vFault simulation _vTest generation _vTest compression _vFEAS |
||
| 942 | _cBK | ||
| 999 |
_c15295 _d15295 |
||