000			00596nam a22001457a 4500
020			_a9788126519316 (pbk)
082			_a621.392 _bPAD
100			_aPadmanabhan, T.R. _aB. Bala Tripura Sundari
245			_aDesign through verilog HDL
260			_aNew Delhi _bWiley India (P.) Ltd. _c2013
300			_axii, 455 p. _b: ill. _c; 23 cm.
500			_aIncludes bibliographical references and index
650			_aVerilog-Computer hardware description languages _vSwitch level modeling _vGate level modeling _vLogic values _vLanguage construction _vBehavioral modeling _vVLSI design _vFEAS
942			_cBK
999			_c15728 _d15728