| 000 | 00575nam a22001577a 4500 | ||
|---|---|---|---|
| 999 |
_c3569 _d3569 |
||
| 020 | _a9788181283177 (pbk) | ||
| 082 |
_a621.395 _bSHE |
||
| 100 | _aSherwani, Naveed A. | ||
| 245 | _aAlgorithms for VLSI physical design automation | ||
| 260 |
_aNew Delhi _bSpringer (India) Private Limited. _c1999 |
||
| 300 |
_axv, 572 p. _b: ill. _c; 22 cm. |
||
| 500 | _aIncludes index. | ||
| 650 |
_aAlgorithms _vFloorplanning pin assignment _vClock power routing _vVLSI design _vTransistor fundamentals _vFabrication process _vGlobal routing _vFEAS |
||
| 942 | _cBK | ||