000			00532nam a22001457a 4500
020			_a9812531319 (pbk)
082			_a621.392 _bPAD
100			_aPadmanabhan, T.R. _aB. Bala Tripura
245			_aDesign through verilog HDL
260			_aCanada _bIEEE Press _c2004
300			_axii, 455 p. _b: ill. _c; 22 cm.
500			_aIndex Included.
650			_aVerilog-Computer hardware description languages _vVLSI design _vVerilog _vLogic values _vScalars and vectors _vSwitch level modeling _vBehavioural modeling _vFEAS
942			_cBK
999			_c3615 _d3615